NAND Flash
Background information
NAND flash is a combination of a not gate and a and gate hence the name N-AND, it functions completely differently to platter based storage such as a hard drive.
as there are no moving parts at all, (not count the screws to attach the drive to its case).
Similarly to how a Hard drive stores data by changing an area of a magnetized disk polarity to represent either a binary figure(0 or 1), NAND memory
used electrons caught within an electrically charged trap (flowing gate) to represent a binary figures. With a full trap representing a 1 (high/true) and an empty trap representing a 0 (Low/false).
Due to the sensitivity of the materials used and the level of current used to empty and fill the gates, a singular gate can not be changed as it drastically shortens the lifespan of the gate and trap
meaning that a group of pages (block) must be changed at the same time. Making the smallest storage aspect a page but the smallest editable aspect a block (typically 64 pages in one block)
NAND is made up Fourth main sections
Physical NAND flash layer
- Integrated circuit-The silicon chip which physically holds all the components
- NAND memory array-Where the data is physically stored on the NAND chip
- Cells-The smallest unit of storage on a NAND chip (houses the floating-gate transistors that store the charge that represents the data)
- Page-Made of up cells, pages typically hold around 2-16killobtyes(KB) each.
- Blocks-typically made up of 64–256 Pages (depending on size of the chip, is the smallest addressable (editable) part of the storage in order to avoid
significantly shortening the life span of a chip, due to how cells function - Floating gate transistors-A transistor that stores a charge to represent either a 1 (has a charge, high) or a 0 (no charge, low) similar to how an HDD uses magnetic polarities
to define a 1 or a 0 - Sense amplifiers-Reads the charge in the floating gate transistor by detecting the difference in voltage, then amplifies the signal for further processes.
- Row and column decoders
- Row-Selects the row in the NAND memory array that needs to be accessed, then activates the appropriate Worldline
- Column-Selects the correct Colum within the selected row in the NAND memory array that needs to be accessed, then directs the data or address bus to the Colum.
- Charge pumps-Turns the low voltage into the high voltage that is required to program (write)/erase the required memory cells.
Flash controller layer
- Flash controller firmware-Operates and manages all the parts of the NAND chip/s on the board (holds the FTL)
- Protocol interface controller-Handles the commination between the internal NAND protocols and the external protocols such as USB or SD (Typically only found on monolithic storage devices
- Direct Memory Access DMA engine-Handles the transfer of data between the NAND memory and the OS memory
- Encryption support-Handles the encryption and decryption of data on the NAND chip/s(if encryption is enabled) to ensure no unauthorized access
Flash translation layer(FTL)-See section 6 for more detail
- Block mapping (logical block address(LBA)- The block mapping is responsible for mapping the logical blocks (digital) to blocks that are physically on the NAND chips themselves,
as unlike hard drive, information is typically stored across multiple locations/chips (if multiple chips are present) especially when sectors begin to wear out and need to be replaced
by ones from the spare area. - Wear levelling- It spreads the wear across the entire memory blocks, to reduce the wear on one set of blocks, by spreading across the dies, wear levelling improves the lifetime of the chips.
- Bad block management- as the name suggests, it's responsible for managing any damaged or unusable blocks then remaps functional blocks from the spare area in the place of the damaged ones.
- Garbage collection- Responsible for clearing up any unused data blocks which it deems as *invalid data (any duplicates, or artifacts from deleted files)merging valid data into spaces within other blocks
then deletes the invalid data ready for block reclamation. - Block reclamation-the first part of block reclamation has already occurred thanks to garbage collection, once the valid and invalid data has been sorted, block reclamation then marks the now empty and healthy
blocks as free, ready for new data to be written too it.
NAND interface layer
- The Open NAND Flash interface(ONPI) protocol-this protocol is responsible for setting the communication standards between the NAND chips themselves and the controllers on the board of the device e.g. SSD, pen drive or SD card
by standardizing the commination protocol, it ensures that NAND chips and controllers which function together, ever if they are made by two different brands. - Bus interface-The physical data lanes that transfer data between the NAND chips and the controller and or the OS itself.
- Data/address latches, command queues-These are signals that data and addresses are attached too respectively during read and write operations.
Command queues are used to process the commands in the most efficient manner. - Clock and power management- Responsible for managing the clock signals and the power required, to ensure that there is always enough power for the operations required and that the clock runs consistently
Ball grid array(BGA) and Surface mount Technology(SMT)
BGA and SMT are the two most common ways that component connects to a PCB itself, there is no best method, each one has its own pros and cons which will be discussed below.
Ball grid array(BGA)
BGA is made up of two flat copper pads on both the component(e.g a NAND chip) then a ball of solder is melted on each pan which connects the PCB to the component
. BGA is standard for most storage chips except for Thin small outline package(TSOP) and its variants, due to the increased in count and reduced form factor as unlike SMT,
BGA connectors are located on the bottom of a component like this.
Figure 1- BGA pads on device and component
Due to the fact that the BGA connections are located on the underside of the chip this makes it more awkward to desolder, and require a hot air station to successfully desolder a BGA chip.
Surface mount Technology(SMT)
SMT works by soldering a metal "leg" or pin to a copper pad on to the PCB with meltable conductive solder, unlike BGA SMT connectors are out typically located on the sides of the component. Please see
for how to work with this style of chip
Flow chart of order of operations
Insert a flow chart of steps and actions for each task (create using diagram)
Related Topics
Topics such as desoldering to chip off or firmware dumping for disk PCB repairs
Further reading
External references in wiki references can just be cited through the keyword link
- Reference 1: NAND flash data recovery cookbook(free)
- Reference 2: BGA and SMT
- Reference 3: floating gate transistor (FGT)
- Reference 4: Inside NAND Flash Memories(The most compressive guide on NAND)
- Reference 5: Nand Flash Memory Technologies(not as detailed but covers 3D NAND)
(Inside NAND Flash Memories is still recommended despite being older)