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<h2>Physical NAND flash layer</h2>
<h2>Physical NAND flash layer</h2>
<ul>
<ul>
<li>NAND memory array-</li>
<li>Integrated circuit-The silcon chip which physcially holds all the components </li>
<li>Floating-gate transistors-</li>
<li>NAND memory array-Where the data is physcially stored on the NAND chip</li>
<li>Sense amplifiers-</li>
<li>Cells- The smallest unit of storage on a NAND chip(houses the floating-gate transistors that store the charage that represents the data)</li>
<li>Row and column decoders-</li>
<li>Page- Made of up cells pages typcially hold around 2-16killobtyes(KB) each.</li>
<li>Charge pumps-</li>
<li>Blocks- typically made up of 64-256 Pages(depending on size of the chip, is the smallest addressable(editiable) part of the storage in order to avoid</br>
<li>Integrated circuit-</li>
significantly shortening the life span of a chip, due to how cells function</li>
<li>Floating gate transistors-A transistor that stores a charge to represent either a 1(has a charge,high) or a 0(no charge,low) similar to how a HDD uses magnetic polarities</br>
to define a 1 or a 0</li>
<li>Sense amplifiers-Reads the charge in the floating gate transistor by detecting the difference in voltage, then amplifies the signal for further processes.</li>
<li>Row and column decoders</li>
<li>Row-Selects the row in the NAND memory array that needs to be accessed, then activates the appropriate Worldline</li>
<li>Column-Selects the correct Colum within the selected row in the NAND memory array that needs to be accessed, then directs the data or address bus to the Colum. </li>
<li>Charge pumps-Turns the low voltage into the high voltage that is required to program (write)/erase the required memory cells.</li>
 
</ul>
</ul>
<h2>Flash controller layer</h2>
<h2>Flash controller layer</h2>
<ul>
<ul>
<li>Flash controller firmware-</li>
<li>Flash controller firmware-Operates and manages all the parts of the NAND chip/s on the board (holds the FTL)</li>
<li>Protocol interface controller-(when used with USB, SD)</li>
<li>Protocol interface controller-Handles the commination between the internal NAND protocols and the external protocols such as USB or SD (Typically only found on monolithic storage devices</li>
<li>DMA engine-</li>
<li>Direct Memory Access DMA engine-Handles the transfer of data between the NAND memory and the OS memory</li>
<li>Encryption support-</li>
<li>Encryption support-Handles the encryption and decryption of data on the NAND chip/s(if encryption is enabled) to ensure no unauthorized access</li>
<li>Error handling and wear levelling -</li>
</ul>
</ul>
<h2>Flash translation layer(FTL)-See <a href="https://datarecoverywiki.com/index.php/Flash_Translation_layer(FTL)">section 6</a> for more detail</h2>
<h2>Flash translation layer(FTL)-See <a href="https://datarecoverywiki.com/index.php/Flash_Translation_layer(FTL)">section 6</a> for more detail</h2>
Line 153: Line 160:
<h2>NAND interface layer</h2>
<h2>NAND interface layer</h2>
<ul>
<ul>
<li>ONPI protocol -<li>
<li>ONPI protocol- <li>
<li>Bus interface-</li>
<li>Bus interface-</li>
<li>Data/address latches, command queues-</li>
<li>Data/address latches, command queues-</li>

Revision as of 14:51, 20 February 2025

Data Recovery Resources

Background information

NAND flash is a combination of a not gate and a and gate hence the name N-AND, it functions completely differently to platter based storage such as a hard drive.
as there are no moving parts at all, (not count the screws to attach the drive to its case).
Similarly to how a Hard drive stores data by changing an area of a magnetized disk polarity to represent either a binary figure(0 or 1), NAND memory
used electrons caught within an electrically charged trap(flowing gate) to represent a binary figures. With a full trap represting a 1(high/true) and an empty trap repenstiving a 0(Low/false).
Due to the sensitivity of the martials used and the level of current used to empty and fill the gates, a singular gate can not be changed as it drastically shortens the lifespan of the gate and trap
meaning that a group of pages (block) must be changed at the same time. Making the smallest storage aspect a page but the smallest editable aspect a block (typically 64 pages in one block)
NAND is made up Fourth main sections

Physical NAND flash layer

  • Integrated circuit-The silcon chip which physcially holds all the components
  • NAND memory array-Where the data is physcially stored on the NAND chip
  • Cells- The smallest unit of storage on a NAND chip(houses the floating-gate transistors that store the charage that represents the data)
  • Page- Made of up cells pages typcially hold around 2-16killobtyes(KB) each.
  • Blocks- typically made up of 64-256 Pages(depending on size of the chip, is the smallest addressable(editiable) part of the storage in order to avoid
    significantly shortening the life span of a chip, due to how cells function
  • Floating gate transistors-A transistor that stores a charge to represent either a 1(has a charge,high) or a 0(no charge,low) similar to how a HDD uses magnetic polarities
    to define a 1 or a 0
  • Sense amplifiers-Reads the charge in the floating gate transistor by detecting the difference in voltage, then amplifies the signal for further processes.
  • Row and column decoders
  • Row-Selects the row in the NAND memory array that needs to be accessed, then activates the appropriate Worldline
  • Column-Selects the correct Colum within the selected row in the NAND memory array that needs to be accessed, then directs the data or address bus to the Colum.
  • Charge pumps-Turns the low voltage into the high voltage that is required to program (write)/erase the required memory cells.

Flash controller layer

  • Flash controller firmware-Operates and manages all the parts of the NAND chip/s on the board (holds the FTL)
  • Protocol interface controller-Handles the commination between the internal NAND protocols and the external protocols such as USB or SD (Typically only found on monolithic storage devices
  • Direct Memory Access DMA engine-Handles the transfer of data between the NAND memory and the OS memory
  • Encryption support-Handles the encryption and decryption of data on the NAND chip/s(if encryption is enabled) to ensure no unauthorized access

Flash translation layer(FTL)-See section 6 for more detail

  • Block mapping (logical block address(LBA)-
  • Wear levelling-
  • Bad block management-
  • Garbage collection-
  • Block reclamation-

NAND interface layer

  • ONPI protocol-
  • Bus interface-
  • Data/address latches, command queues-
  • Clock and power management-

How floating gate transistors work

Teleporting quantum magic Quantum tunnelling effect

Ball grid array(BGA) and Surface mount Technology(SMT)

Flow chart of order of operations

Insert a flow chart of steps and actions for each task (create using diagram)

Related Topics

Topics such as desoldering to chip off or firmware dumping for disk PCB repairs

Further reading

External references in wiki references can just be cited through the keyword link

  1. Reference 1: NAND flash data recovery cookbook(free)
  2. Reference 2: paper on the actual architecture of a NAND chip functions
  3. Reference 3: BGA and SMT

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