NAND Flash: Difference between revisions
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<li>Reference 1: <a href="https://www.adreca.net/NAND-Flash-Data-Recovery-Cookbook.pdf">NAND flash data recovery cookbook(free)</a></li> | <li>Reference 1: <a href="https://www.adreca.net/NAND-Flash-Data-Recovery-Cookbook.pdf">NAND flash data recovery cookbook(free)</a></li> | ||
<li>Reference 2: <a href="#">paper on the actual architecture of a NAND chip functions</a></li> | <li>Reference 2: <a href="#">paper on the actual architecture of a NAND chip functions</a></li> | ||
<li>Reference 3: <a href="https://ipcb.eu/bga/">BGA and SMT</a></li> | |||
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Revision as of 14:18, 20 February 2025
Background information
NAND flash is a combination of a not gate and a and gate hence the name N-AND, it functions completely differently to platter based storage such as a hard drive.
as there are no moving parts at all, (not count the screws to attach the drive to its case).
Similarly to how a Hard drive stores data by changing an area of a magnetized disk polarity to represent either a binary figure(0 or 1), NAND memory
used electrons caught within an electrically charged trap(flowing gate) to represent a binary figures. With a full trap represting a 1(high/true) and an empty trap repenstiving a 0(Low/false).
Due to the sensitivity of the martials used and the level of current used to empty and fill the gates, a singular gate can not be changed as it drastically shortens the lifespan of the gate and trap
meaning that a group of pages (block) must be changed at the same time. Making the smallest storage aspect a page but the smallest editable aspect a block (typically 64 pages in one block)
NAND is made up Fourth main sections
Physical NAND flash layer
- NAND memory array-
- Floating-gate transistors-
- Sense amplifiers-
- Row and column decoders-
- Charge pumps-
- Integrated circuit-
Flash controller layer
- Flash controller firmware-
- Protocol interface controller-(when used with USB, SD)
- DMA engine-
- Encryption support-
- Error handling and wear levelling -
Flash translation layer(FTL)-See section 6 for more detail
- Block mapping (logical block address(LBA)-
- Wear levelling-
- Bad block management-
- Garbage collection-
- Block reclamation-
NAND interface layer
- ONPI protocol -
- Bus interface-
- Data/address latches, command queues-
- Clock and power management-
How floating gate transistors work
Teleporting quantum magic
Ball grid array(BGA) and Surface mount Technology(SMT)
Flow chart of order of operations
Insert a flow chart of steps and actions for each task (create using diagram)
Related Topics
Topics such as desoldering to chip off or firmware dumping for disk PCB repairs
Further reading
External references in wiki references can just be cited through the keyword link
- Reference 1: NAND flash data recovery cookbook(free)
- Reference 2: paper on the actual architecture of a NAND chip functions
- Reference 3: BGA and SMT