Flash Translation layer(FTL): Difference between revisions
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<h1> Background information </h1> | <h1> Background information </h1> | ||
<p> | <p> The Flash Translation Layer acts as the name suggests a translation layer between the physical NAND chips and the digital operating system that runs from them.</br> | ||
<br> | The following pages of this segment go into deeper detail of each aspect of the FTL, but an overview of each aspect are as follows | ||
<ul> | |||
<li>Block Mapping - Is responsible for mapping the digital data to the physical location on the chip dies | |||
</br> since there is not always(if ever) 1:1 relation to where data is stored digital and where it is storaged digitally.</li> | |||
<li>Wear Levelling- Due to the nature of how Nand functions each cell within the chip has a limited lifespan, | |||
</br> wear leveling prevent execes wear on certain areas</li> | |||
<li>Bad Block Management - Once a area does have excess wear or simply does not function correctly | |||
</br>its located is noted by the FTL and not used with the digital addresses being relocated to a healthy area of the storage</li> | |||
<li>Garbage collection- as the name suggests this aspect is responible for clearing blocks that have previously been written too | |||
</br> but are now unused. or need to store different information.</li> | |||
<li>Block Reclamation- is responsible for moving blocks back to the list of avaible space after Garbage collection has erased them</li> | |||
<h1 id="section0">What tools you will need</h1> | <h1 id="section0">What tools you will need</h1> | ||
<i> Items are not listed in any particular order </i> | <i> Items are not listed in any particular order </i> | ||
Revision as of 14:15, 14 January 2025
Contents
Background information
The Flash Translation Layer acts as the name suggests a translation layer between the physical NAND chips and the digital operating system that runs from them.
The following pages of this segment go into deeper detail of each aspect of the FTL, but an overview of each aspect are as follows
- Block Mapping - Is responsible for mapping the digital data to the physical location on the chip dies
since there is not always(if ever) 1:1 relation to where data is stored digital and where it is storaged digitally. - Wear Levelling- Due to the nature of how Nand functions each cell within the chip has a limited lifespan,
wear leveling prevent execes wear on certain areas - Bad Block Management - Once a area does have excess wear or simply does not function correctly
its located is noted by the FTL and not used with the digital addresses being relocated to a healthy area of the storage - Garbage collection- as the name suggests this aspect is responible for clearing blocks that have previously been written too
but are now unused. or need to store different information. - Block Reclamation- is responsible for moving blocks back to the list of avaible space after Garbage collection has erased them
- Test
- Test
- 1.test
- 2.test
- 3.test
- Reference 1: Source details
- Reference 2: Source details
What tools you will need
Items are not listed in any particular orderRequired
Optional but useful
Uses of this skill
Step-by-step guide with images
Insert step-by-step walkthrough with images and summary text here
Flow chart of order of operations
Insert a flow chart of steps and actions for each task (create using diagram)
Troubleshooting/tips and tricks
Fixes to any common issues that were encountered or could be easily encountered
Related Topics
Topics such as desoldering to chip off or firmware dumping for disk PCB repairs
Further reading
External references in wiki references can just be cited through the keyword link