Join Action Test Group(JTAG)
Contents
Background information
This page will cover the Join Action Test group(JTAG) protocol also known as IEEE 1149, how it functions, how to communicate with a device over it, and where to find the ports.
JTAG headers typically look like a row or square of sliver headers or pads with phrases such as JTAG,TDI,TDO on the silkscreen.
FULL TAG PIN OUT -------------------------------------------Reduced PIN OUT
1. TDI (Test Data In) ----------------------------------------TMSC (Test Serial Data)
2. TDO (Test Data Out)
3. TCK (Test Clock)------------------------------------------TCK (Test Clock)
4. TMS (Test Mode Select)
5. TRST (Test Reset) optional.
6. GND
Checking for activity on pins
If the pin lay out is not available in either the device datasheet or having been previously reversed by another person/group,
Then there are other ways of analysing the activity of each pin to determine what each pin is.
Voltages levels of pins
- TDI, TDO, TMS, TCK - can function at the 1.8v,3.3v or 5v range
- GND - 0V
- VCC - system voltage level 3.3v or 5v use of Debugging tools hardware
- OpenOCD
- Seggger J-Link
- jtagulator
- Jtag chain
- clock signals - TCK
- Data transfers - TDI, TDO, TMS
Step-by-step guide with images
Insert step-by-step walkthrough with images and summary text here
Flow chart of order of operations
Insert a flow chart of steps and actions for each task (create using diagram)
Troubleshooting/tips and tricks
Fixes to any common issues that were encountered or could be easily encountered
Related Topics
Topics such as desoldering to chip off or firmware dumping for disk PCB repairs
Further reading
External references in wiki references can just be cited through the keyword link